Technological and economic trend
Moore's
Law
For decades, the economically practical complexity of integrated circuits rose exponentially. The trend was not a law of nature: it was sustained by lithography, device physics, manufacturing learning, design automation, capital investment, and coordinated industry roadmaps.
Exponential progress hides inside ordinary time.
Choose a starting chip, elapsed time, and doubling period. The model shows why a modest-looking cadence creates enormous differences across generations.
A log scale turns repeated doublings into a straight line. Each equal vertical step represents multiplication, not addition.
The original claim was narrower and more interesting.
In 1965 Gordon Moore examined the number of components that could be placed on an integrated circuit at minimum cost per component. He observed an approximately annual doubling and projected the trend for roughly a decade.[1] The familiar two-year cadence came from his 1975 reassessment, not from the original article.[2]
Moore did not claim that every chip, computer, workload, or user experience would double on one schedule. Component count, transistor density, cost per transistor, clock frequency, energy efficiency, and application performance are different measurements.
"Moore's Law worked because an observation became a coordination device for an entire industrial system."
More components were useful only when they became economical.
Early integrated circuits faced a tradeoff. Adding components spread packaging and processing costs across more functions, but larger and more complex dies were more vulnerable to manufacturing defects. Moore's curve concerned the moving minimum between those pressures.
More functions share fabrication, packaging, and assembly.
Larger or defect-sensitive designs lose more value when a die fails.
Process control and volume improve yield and reduce unit cost.
Technology shifts the cheapest useful complexity upward.
No single invention sustained the curve.
The trend required a coupled production system. Improvements in one layer created pressure and opportunity in the others.
Lithography
Shorter wavelengths, better optics, masks, resist, and process control patterned smaller features.
Device physics
New gate structures, materials, and transistor geometries controlled leakage and electrostatics.
Manufacturing
Cleanliness, metrology, yield learning, and larger wafers turned designs into volume products.
EDA and architecture
Automation made it possible to specify, verify, and route designs humans could not manage manually.
Capital
Enormous fabrication and research investments were justified by expected future markets.
Roadmaps
Shared targets coordinated equipment, materials, foundries, designers, and customers.
Dennard scaling
The 1974 MOSFET scaling analysis described how smaller devices could improve density and speed while scaling voltage and current.[3] For years, density gains arrived with favorable power behavior.
The trend changed its mechanism while keeping its reputation.
Planar processing and monolithic integration create a scalable manufacturing platform.
Moore charts economically favorable component complexity and projects ten years forward.
Dennard and colleagues formalize MOSFET scaling; Moore revises the longer-run cadence toward two years.
CMOS, optical scaling, EDA, and global supply chains compound density and cost improvements.
Voltage scaling weakens. Clock-frequency growth slows and multicore designs become central.
FinFETs, gate-all-around devices, accelerators, chiplets, 2.5D/3D packaging, and specialized memory broaden the path.
The historical product figures above follow Intel's museum material; they illustrate the scale change but do not form a clean scientific dataset because product classes and functions differ.[7]
Density continued, but its companions separated.
The phrase "Moore's Law is dead" is usually underspecified. Different curves slowed at different times. The end of automatic clock-frequency gains is not identical to the end of density improvement.
Device structures and patterning still raise density, with growing difficulty and cost.
Power and thermal limits ended the simple frequency-scaling era.
Advanced process and design costs complicate the historical economic payoff.
Architecture, memory, parallelism, and software dominate realized benefit.
Scaling moved from one dimension to many.
The 2024 IEEE IRDS roadmap treats continued scaling as a portfolio of device, interconnect, integration, and design challenges rather than a single shrinking number.[8]
New transistor geometry
FinFET and gate-all-around structures improve electrostatic control as dimensions shrink.
3D integration
Stacking logic, cache, and memory increases functional density without relying only on planar shrink.
Chiplets
Functions can use different process nodes and be combined with high-bandwidth die-to-die links.
Specialization
GPUs, AI accelerators, media engines, and domain-specific units trade generality for efficiency.
Data proximity
High-bandwidth and stacked memory attack energy and latency spent moving data.
Parallel execution
Compilers and algorithms must expose concurrency to benefit from wider and heterogeneous hardware.
The UCIe Consortium defines an open die-to-die interconnect intended to support an interoperable chiplet ecosystem.[9] This is one example of scaling becoming a packaging and system-integration problem.
Always ask: which curve?
"Computers double in speed."
Performance depends on workload, architecture, memory, power, and software.
"Eighteen months was Moore's original law."
The 1965 projection used an annual cadence; the 1975 revision moved toward two years.
"It is a law of physics."
It is an empirical technological-economic trend sustained by investment and coordination.
"One node name measures transistor size."
Modern process labels are product names, not one universal physical dimension.
"More transistors guarantee value."
Unused complexity can raise cost, verification burden, and energy without improving the task.
"The law has one death date."
Density, cost, frequency, energy, and performance trends diverged at different times.
Sources and further reading.
Original papers, technical roadmaps, official histories, and standards organizations are prioritized.
- Gordon E. Moore (1965) - Cramming More Components onto Integrated CircuitsThe original Electronics article on component complexity and minimum component cost.computerhistory.org/.../Moore_1965_Article.pdf
- Gordon E. Moore (1975) - Progress in Digital Integrated ElectronicsThe reassessment that separated early one-time factors from the longer-run doubling cadence.IEEE IEDM Technical Digest, 1975
- Dennard et al. (1974) - Design of Ion-Implanted MOSFETs with Very Small Physical DimensionsThe foundational MOSFET scaling paper.doi.org/10.1109/JSSC.1974.1050511
- Computer History Museum - Moore's Law at 50Historical account of the original projection, economic framing, and industry coordination.computerhistory.org/blog/moores-law50...
- Computer History Museum - Silicon Engine TimelineDocumented milestones in planar processing, MOS, integrated circuits, CAD, and manufacturing.computerhistory.org/siliconengine/timeline/
- Intel - Moore's Law Press KitIntel's account of the 1965 forecast, 1975 revision, and present advanced-device strategy.newsroom.intel.com/press-kit/moores-law
- Intel Museum - Transistors to TransformationsOfficial historical processor examples with transistor count, process, clock, and product context.intel.com/.../museum-transistors-to-transformations...
- IEEE IRDS (2024) - More Moore RoadmapCurrent technical roadmap for device, interconnect, integration, and density challenges.irds.ieee.org/images/files/pdf/2024/2024IRDS_MM.pdf
- UCIe Consortium - Specifications and ResourcesOfficial resources for the open die-to-die interconnect standard and chiplet ecosystem.uciexpress.org/ucie-resources
- Gordon Moore (1997) - An Update on Moore's LawMoore's retrospective discussion of economics, feature scaling, reliability, and physical limits.intel.com/pressroom/archive/speeches/GEM93097.HTM